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| 74F377 Octal D-Type Flip-Flop with Clock Enable April 1988 Revised September 2000 74F377 Octal D-Type Flip-Flop with Clock Enable General Description The 74F377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. Features s Ideal for addressable register applications s Clock enable for address and data synchronization applications s Eight edge-triggered D-type flip-flops s Buffered common clock s See 74F273 for master reset version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version Ordering Code: Order Number 74F377SC 74F377SJ 74F377PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code. Logic Symbols Connection Diagram IEEE/IEC (c) 2000 Fairchild Semiconductor Corporation DS009525 www.fairchildsemi.com 74F377 Unit Loading/Fan Out U.L. Pin Names D0-D7 CE CP Q0-Q7 Description HIGH/LOW Data Inputs Clock Enable (Active LOW) Clock Pulse Input Data Outputs 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA -1 mA/20 mA Mode Select-Function Table Inputs Operating Mode CP Load "1" Load "0" Hold (Do Nothing) Output Dn h I X X Qn H L No Change No Change CE I I h H X H = HIGH Voltage Level h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition L = LOW Voltage Level I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition X = Immaterial = LOW-to-HIGH Clock Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74F377 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V -0.5V to VCC -0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL IOS ICEX VID IOD ICCH ICCL Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Output Short-Circuit Current Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Power Supply Current 35 44 4.75 3.75 46 56 -60 10% VCC 5% VCC 10% VCC 2.5 2.7 0.5 5.0 7.0 -0.6 -150 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V V A A mA mA A V A mA Min Min Min Max Max Max Max Max 0.0 0.0 Max VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -1 mA IOL = 20 mA VIN = 2.7V VIN = 7.0V VIN = 0.5V VOUT = 0V VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded CP = Dn = MR = HIGH 3 www.fairchildsemi.com 74F377 AC Electrical Characteristics TA = +25C Symbol Parameter Min fMAX tPLH tPHL Maximum Clock Frequency Propagation Delay CP to Qn 130 3.0 4.0 7.0 9.0 VCC = +5.0V CL = 50 pF Typ Max TA = -55C to +125C VCC = +5.0V CL = 50 pF Min 85 2.0 3.0 8.5 10.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 105 2.5 3.5 7.5 9.0 Max MHz ns Units AC Operating Requirements TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP Setup Time, HIGH or LOW CE to CP Hold Time, HIGH to LOW CE to CP Clock Pulse Width, HIGH or LOW 3.0 3.5 0.5 1.0 4.1 3.5 0.5 2.0 6.0 6.0 Max TA = -55C to +125C VCC = +5.0V Min 3.5 4.0 1.0 1.0 4.0 5.0 1.5 2.5 5.0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 3.0 3.5 0.5 1.0 4.1 4.0 0.5 2.0 6.0 6.0 Max ns ns ns ns ns Units www.fairchildsemi.com 4 74F377 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74F377 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74F377 Octal D-Type Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com www.fairchildsemi.com |
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